METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE

ABSTRACT

A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.

This divisional application claims priority to co-pending U.S. patentapplication Ser. No. 12/128,955 entitled METHODS OF INTEGRATING REVERSEeSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE, filed onMay 29, 2008, the contents of which are hereby incorporated by referencein their entirety.

BACKGROUND

1. Technical Field

The disclosure relates generally to integrated circuit (IC) chipfabrication, and more particularly, to a high-k/metal gate transistorfabrication.

2. Background Art

To enable high performance complementary metal-oxide semiconductor(CMOS) technologies such as high dielectric constant (high-k) and metalgate solutions, a band-edge metal is required in the channel for eachtransistor to maximize performance and provide threshold voltages (Vt)appropriate for low voltage, low power technologies. Different band-edgemetals in the channels have been shown to work for n-type field effecttransistors (NFETs) and p-type FETs (PFETs). One challenge relative tofabricating these devices is preventing shifts in Vt during processingthat occurs after initial formation.

Another challenge is to form both NFETs and PFETs together where eachrequires a different, or different concentration of, a band-edge metal.Typically, different, non-compatible, fabrication techniques are used.For example, one technique for certain PFETs includes using a thinepitaxially grown silicon germanium (SiGe) layer grown on top of asingle crystal silicon layer to generate a SiGe channel for the PFET.The SiGe channel enables a shift of voltage from mid-gap to band-edgefor the metal gate of the PFET, which improves performance. In contrast,for certain NFETs, a technique referred to as reverse embedded silicongermanium, i.e., reverse eSiGe, uses a plug of SiGe material embeddedunderneath the channel region of the device. The plug advantageouslytensilely stresses the channel region which improves performance of theNFET. Current approaches to integrate both devices use multipleselective epitaxial growth processes for the different SiGe portions.That is, different selective epitaxial processes are used to grow theSiGe channel for PFETs, the SiGe plug for NFETS and perhaps SiGesource/drain regions. In addition, in some cases, an epitaxially grownsilicon cap may be required on the SiGe plug of the NFETs and perhaps onthe SiGe channel of the PFETs. The multiple epitaxial processes presenta number of disadvantages such as added expense and poor throughput. Inaddition, each selective epitaxial growth process required presents achallenge regarding removal of any residual oxide that may form on theepitaxially grown area during exposure to the environment. Morespecifically, each epitaxially grown area may require an aqueoushydro-fluoric acid (HF) pre-clean and an in-situ hydrogen (H₂) pre-bakeprior to subsequent processing to remove any residual oxide, which maycause defects if not adequately removed. Since the temperature of thein-situ H₂ pre-bake must be controlled to prevent damage to anypreviously formed sections, adequate oxide removal is challenging andoftentimes results in non-uniformity issues. Further non-uniformity andcomplexity issues are presented by the selective epitaxial growthprocesses in that the morphology of the sections being formed, and theedge effects of the sections, is defined by the openings into which theepitaxy is performed.

SUMMARY

Methods of integrating reverse embedded silicon germanium (SiGe) on anNFET and SiGe channel on a PFET, and a related structure are disclosed.One method may include providing a substrate including an NFET area anda PFET area; performing a single epitaxial growth of a silicon germanium(SiGe) layer over the substrate; forming an NFET in the NFET area, theNFET including a SiGe plug in a channel thereof formed from the SiGelayer; and forming a PFET in the PFET area, the PFET including a SiGechannel formed from the SiGe layer. As an option, the SiGe layer overthe PFET area may be thinned.

A first aspect of the disclosure provides a method comprising: providinga substrate including an NFET area and a PFET area; performing a singleepitaxial growth of a silicon germanium (SiGe) layer over the substrate;thinning the SiGe layer over the PFET area; forming an NFET in the NFETarea, the NFET including a SiGe plug in a channel thereof formed fromthe SiGe layer; and forming a PFET in the PFET area, the PFET includinga SiGe channel formed from the SiGe layer.

A second aspect of the disclosure provides a method comprising:providing a substrate including an NFET area and a PFET area; performinga single epitaxial growth of a silicon germanium (SiGe) layer over thesubstrate; forming an NFET in the NFET area, the NFET including a SiGeplug in a channel thereof formed from the SiGe layer; and forming a PFETin the PFET area, the PFET including a SiGe channel formed from the SiGelayer.

A third aspect of the disclosure provides a structure comprising: anNFET having an embedded silicon germanium (SiGe) plug in a channelthereof; a PFET having a SiGe channel; and a trench isolation betweenthe NFET and the PFET, wherein the NFET and the PFET are devoid of SiGeepitaxial growth edge effects.

The illustrative aspects of the present disclosure are designed to solvethe problems herein described and/or other problems not discussed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this disclosure will be more readilyunderstood from the following detailed description of the variousaspects of the disclosure taken in conjunction with the accompanyingdrawings that depict various embodiments of the disclosure, in which:

FIG. 1 shows one embodiment of a substrate providing process andepitaxial grown SiGe layer according to the disclosure.

FIGS. 2-7 show other embodiments of the FIG. 1 process according to thedisclosure.

FIG. 8-10 show optional thinning processes according to the disclosure.

FIGS. 11-16 show processes for forming an NFET and PFET according to thedisclosure, with FIG. 16 showing a structure according to thedisclosure.

FIGS. 17-18 show an optional process according to the disclosure, withFIG. 18 showing a structure according to the disclosure.

It is noted that the drawings of the disclosure are not to scale. Thedrawings are intended to depict only typical aspects of the disclosure,and therefore should not be considered as limiting the scope of thedisclosure. In the drawings, like numbering represents like elementsbetween the drawings.

DETAILED DESCRIPTION

The disclosure relates to methods of forming, and related structure, asingle epitaxial growth of a silicon germanium (SiGe) layer on both ann-type field effect transistor (NFET) area and p-type FET (PFET) area,which allows for process simplification. The thickness and compositionof the SiGe layer in the PFET area can be separately controlled in anoptional thinning process.

Referring to the drawings, FIG. 1 shows a first process includingproviding a substrate 100 including an NFET area 102 and a PFET area102. NFET area 102 and PFET area 104 indicate regions of substrate 100that will eventually have NFETs and PFETs formed thereon. As understood,the position of areas 102, 104 may be switched. Substrate 100 mayinclude but is not limited to silicon, germanium, silicon germanium,silicon carbide, and those consisting essentially of one or more III-Vcompound semiconductors having a composition defined by the formulaAl_(X1) Ga_(X2)In_(X3)As_(Y1)P_(Y2)N_(Y3)Sb_(Y4), where X1, X2, X3, Y1,Y2, Y3, and Y4 represent relative proportions, each greater than orequal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relativemole quantity). Other suitable substrates include II-VI compoundsemiconductors having a composition Zn_(A1)Cd_(A2)Se_(B1)Te_(B2), whereA1, A2, B1, and B2 are relative proportions each greater than or equalto zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore,a portion or entire semiconductor substrate may be strained.

FIG. 1 also shows performing a single epitaxial growth of a silicongermanium (SiGe) layer 110 over substrate 100. SiGe layer 110 mayinclude any required concentration ratio of Si to Ge, and may includeconcentration gradients. Epitaxial growth, as understood in the art,includes an ordered crystalline growth on a monocrystalline material,and may be grown from gaseous or liquid precursors. Since the underlyingmaterial acts as a seed material, the grown layer takes on a latticestructure and orientation identical to those of the underlying material.However, the different composition of the epitaxial layer leads tolattice constant mismatch at the interface, and hence both the substrateand the epitaxially grown layer are strained. FIG. 2 shows forming atrench isolation 112, such as a shallow trench isolation (STI), afterformation of SiGe layer 110. Trench isolation 112 may be formed in anynow known or later developed fashion, e.g., depositing a photoresist,patterning the photoresist, etching to form a trench, depositing adielectric such as silicon oxide (SiO₂), and planarizing.

FIGS. 3-4 show an alternative embodiment in which trench isolation 112is formed in substrate 100 (FIG. 3) prior to performing the singleepitaxial growth of SiGe layer 110 over substrate 100 (FIG. 4). As shownin FIG. 4, due to the presence of trench isolation 112, SiGe layer 110is selectively grown from the remaining exposed substrate 100.

FIGS. 5-6 show an optional process in which a silicon (Si) cap 114 isepitaxially grown over SiGe layer 110, e.g., by turning off thegermanium source. FIG. 5 shows Si cap 114 over the FIG. 2 embodiment(with trench isolation 112 formed after SiGe layer deposition) and FIG.6 shows Si cap 114 over the FIG. 4 embodiment (with trench isolationformed prior to SiGe layer deposition). Si cap 114 may be provided for anumber of reasons, but notably to allow formation of a SiGe plug withina channel of an NFET in NFET area 102, as will be described in greaterdetail herein. In an alternative embodiment, shown in FIG. 7 applied tothe FIG. 2 embodiment only, where Si cap 114 is only required over NFETarea 102, a mask 116, such as a silicon nitride (Si₃N₄) hardmask, may beformed over PFET area 104 such that epitaxial growth of silicon onlyoccurs over NFET area 102.

Note, FIGS. 8-16, unless otherwise stated, show subsequent processingbased on the FIG. 7 embodiment.

FIG. 8 shows an optional process of thinning SiGe layer 110 in PFET area104. An initial stage of this process includes forming a mask 120 suchas a silicon nitride (Si₃N₄) hardmask over NFET area 102. Subsequentprocessing to thin SiGe layer 110 in PFET area 104 may occur in a numberof ways. In one embodiment, shown in FIG. 8, the thinning process mayinclude performing a reactive ion etch (RIE) 122 on PFET area 104,resulting in the thinning of SiGe layer 110. In another embodiment, alsoshown in FIG. 8, the thinning process may include performing a wet etch124, such as an aqueous mixture of ammonium hydroxide (NH₄OH) andhydrogen peroxide (H₂O₂), which may also be referred to as “standardclean-1” or “SC-1”, resulting in the thinning of SiGe layer 110. WhereSi cap 114 is formed over SiGe layer 110 prior to mask 120 forming,e.g., as in FIGS. 5-6, the SC-1 cleaning results in removal of Si cap114 over PFET area 104.

In another embodiment, shown in FIGS. 9-10, the thinning process mayinclude oxidizing PFET area 104, i.e., exposing it to an oxidizingenvironment 126. This embodiment requires Si cap 114 over PFET area 104,as shown in FIGS. 5-6. This process has the added advantage that it can,independent of NFET area 102, increase a germanium (Ge) concentration inSiGe layer 110 over PFET area 104. In particular, oxidation 126 allowsremoval of Si cap 114 over PFET area 104 and, since germanium (Ge)resists incorporation into any oxide, the oxidation causes the germanium(Ge) to move further into a SiGe layer 132 over PFET area 104,increasing Ge concentration therein. This movement of germanium (Ge) maybe referred to as “snowplowing”. Removing oxide 128, e.g., using ahydrofluoric (HF) acid bath 130, after the oxidation results in athinner and higher Ge concentration SiGe layer 132 over PFET area 104(compared to SiGe layer 110 over NFET area 102). As will be described ingreater detail herein, SiGe layer 132 eventually becomes a channel of aPFET.

Removal of mask 120 from NFET area 102, e.g., by a RIE or wet etch,finalizes any of the above-described thinning processes.

At this stage, if trench isolation 112 and/or Si cap 114 has not alreadybeen formed, one or both of them may be formed. That is, in onealternative embodiment to that described above, trench isolation 112forming occurs after the thinning (FIGS. 8-9). For example, by maskingPFET area 104 and epitaxially growing Si cap 114, and/or by performingthe above-described trench isolation forming processes.

In another alternative embodiment, an aqueous HF clean followed by a lowtemp (700° C.-900° C.) in-situ H₂ prebake may be performed at this stage(FIGS. 11-16).

FIGS. 11-16 show forming an NFET 140 (FIG. 16) in NFET area 102 and aPFET 142 (FIG. 16) in PFET area 104. NFET 140 includes a SiGe plug 144in a channel 146 thereof formed from SiGe layer 110 (FIG. 11)(below Sicap 114), and PFET 142 includes a SiGe channel 148 formed from SiGelayer 132 (FIG. 11). NFET 140 and PFET 142 may be formed using any nowknown or later developed techniques. FIG. 11 shows forming gates 150,e.g., metal gates including silicon nitride spacer. FIG. 12 showsrecessing a source/drain region 152 for NFET area 102, e.g., using a RIEwith PFET area 104 masked, and FIG. 13 shows selective silicon (Si) orsilicon carbide (SiC) epitaxial growth of source/drain region 154 forNFET area 102. FIG. 14 shows recessing a source/drain region 156 forPFET area 104, e.g., using a RIE with NFET area 102 masked, and FIG. 15shows selective silicon germanium (SiGe) epitaxial growth ofsource/drain region 158 for PFET area 104. PFET source/drain 158 SiGemay include an intrinsic compressive strain to enhance performance ofPFET 142. FIG. 16 shows NFET 140 and PFET 142. The recessing andepitaxial growth of source/drain regions for NFET 140 and PFET 142 maybe reversed in order.

Turning to FIGS. 17-18, in an alternative embodiment, NFET area 102 maybe etched prior to performing the epitaxial growth of SiGe layer 110.That is, substrate 100 is etched from the situation shown in FIG. 1 suchthat NFET area 102 is lower than PFET area 104. In this manner, a stepdifference between areas 102, 104 that may result in different heightsof NFET 140 and PFET 142 (FIG. 16), may be avoided. The step differencemay range from approximately 10-20 nm, which may impact planarization insome instances. FIG. 18 shows NFET 140 and PFET 142 after using the FIG.17 embodiment. NFET 140 and PFET 142 are substantially at the sameheight.

Referring to FIGS. 16 and 18, a structure according to the disclosuremay include NFET 140 having an embedded silicon germanium (SiGe) plug144 in channel 146 thereof, PFET 142 having SiGe channel 148, and trenchisolation 112 between NFET 140 and PFET 142. SiGe channel 148 and SiGeplug 144 are part of a single SiGe layer 110, 132. In contrast toconventional NFETs and PFETs using reverse embedded SiGe plugs and SiGechannels, NFET 140 and PFET 142 are devoid of SiGe epitaxial growth edgeeffects. More specifically, during multiple selective SiGe epitaxialgrowth, the facets of the openings into which the growth occurs causesconcentrations of silicon and germanium to be different along edges ofthe sections formed. This situation causes problems such as lostperformance, and in the future may prevent morphology correction atadvanced technology dimensions. In contrast, since SiGe layer 110according to the disclosure is formed in a single epitaxial growth,there are no edge effect concerns since the active area and trenchisolation 112 boundary is now defined by the active region RIE insteadof the epitaxial growth's opening facet. The blanket, single epitaxiallayer 110 can be grown with better defectivity and manufacturability(e.g., better uniformity, throughput, lower cost). Consequently,epitaxial opening facet edge effects are eliminated for both NFET 140and PFET 142.

The methods and related structure as described above are used in thefabrication of integrated circuit chips. The resulting integratedcircuit chips can be distributed by the fabricator in raw wafer form(that is, as a single wafer that has multiple unpackaged chips), as abare die, or in a packaged form. In the latter case the chip is mountedin a single chip package (such as a plastic carrier, with leads that areaffixed to a motherboard or other higher level carrier) or in amultichip package (such as a ceramic carrier that has either or bothsurface interconnections or buried interconnections). In any case thechip is then integrated with other chips, discrete circuit elements,and/or other signal processing devices as part of either (a) anintermediate product, such as a motherboard, or (b) an end product. Theend product can be any product that includes integrated circuit chips,ranging from toys and other low-end applications to advanced computerproducts having a display, a keyboard or other input device, and acentral processor.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present disclosure has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the disclosure in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the disclosure. Theembodiment was chosen and described in order to best explain theprinciples of the disclosure and the practical application, and toenable others of ordinary skill in the art to understand the disclosurefor various embodiments with various modifications as are suited to theparticular use contemplated.

1. A structure comprising: an NFET having an embedded silicon germanium(SiGe) plug in a channel thereof; a PFET having a SiGe channel; and atrench isolation between the NFET and the PFET, wherein the NFET and thePFET are devoid of SiGe epitaxial growth edge effects.
 2. The structureof claim 1, wherein the embedded SiGe plug and the SiGe channel are partof a single layer of SiGe.
 3. A structure comprising: an NFET having anembedded silicon germanium (SiGe) plug in a channel thereof; a PFEThaving a SiGe channel, wherein a height of the NFET and a height of thePFET are different; and a trench isolation between the NFET and thePFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growthedge effects.
 4. The structure of claim 3, wherein the embedded SiGeplug and the SiGe channel are part of a single layer of SiGe.
 5. Thestructure of claim 3, wherein the height of the NFET and the height ofthe PFET differ by between about 10 nm and about 20 nm.
 6. An integratedcircuit chip, comprising: at least one structure, including: an NFEThaving an embedded silicon germanium (SiGe) plug in a channel thereof; aPFET having a SiGe channel; and a trench isolation between the NFET andthe PFET, wherein the NFET and the PFET are devoid of SiGe epitaxialgrowth edge effects.
 7. The integrated circuit chip of claim 6, whereinthe embedded SiGe plug and the SiGe channel are part of a single layerof SiGe.
 8. The integrated circuit chip of claim 6, wherein a height ofthe NFET and a height of the PFET are different.
 9. The integratedcircuit chip of claim 8, wherein the height of the NFET and the heightof the PFET differ by between about 10 nm and about 20 nm.